This invention relates to flat panel displays, and more precisely, to the structures of drivers for flat panel displays such as active matrix liquid crystal displays.
Among flat panel displays, liquid crystal displays employing liquid crystal layers as light modulation layers are light, thin, and low-power-consumption, and due to these characteristics, are used in various fields. In particular, active matrix liquid crystal displays employing a switching element for each pixel are rapidly spreading as displays for OA appliances such as personal computers.
In the present active matrix liquid crystal displays, pixel switching elements on an array substrate are usually made of thin-film transistors (TFTs) using amorphous silicon (a-Si) for active layers. Recently marketed are displays employing pixel switching elements made of TFTs that use polysilicon (p-Si) for active layers.
Compared with the a-Si TFTs, the p-Si TFTs have higher electron mobility, and therefore, can be formed in small sizes to provide an advantage of partly forming drivers in a space on a substrate. For example, an entire gate-line driver and part of a data-line driver including shift registers and analog switching elements may be formed on an array substrate, and on an external printed circuit board (PCB), D/A converters, etc., of the data-line driver and a control IC for generating various control signals may be formed.
An improvement in screen resolution requires an improvement in the operation speed and data write speed of a data-line driver. To cope with this, there is a technique to divide pixels to be driven in a horizontal scan period into several large blocks, simultaneously transmit data to the large blocks, and simultaneously process the data. In each of the large blocks, the technique divides data lines into small blocks and sequentially drives the small blocks. This technique is capable of elongating a sampling time that is based on the output of a shift register.
As an example, a screen having a matrix of 1024 pixels in a horizontal direction, i.e., XGA (1024xc3x97768) is considered. Eight pixels (each pixel consisting of three dots, i.e., R, G, and B dots) connected to 24 data lines form a small block. Such small blocks are sequentially scanned at horizontal scan intervals of {fraction (1/32)}, to drive 256 pixels in one horizontal scan period. The 256 pixels correspond to xc2xc (a large block) of the screen. Namely, data for four parallel columns, i.e., 24xc3x974=96 video signals must be supplied for the screen. If there is a driver IC capable of supplying 48 signals, two such driver ICs will be needed.
In this way, a screen may be divided into four large blocks, for which video data are simultaneously sampled and provided. This technique can elongate the sampling time of a shift register four times that of a single shift register that sequentially samples video data for a screen, thereby displaying better images.
If the number of pixels is increased to realize high resolution in the future, the number of data lines simultaneously connected to a screen will be increased. In this case, each large block will be driven with a larger number of driver ICs. Driver ICs involve subtle differences in the output characteristics thereof, even if they are from the same manufacturing lot, and in addition, are connected to wires of different lengths. As a result, the driver ICs show performance offsets. Due to the offsets, the boundaries of each driver IC will appear on a screen even in the same large block.
Even if adjacent driver ICs provide signal voltages of the same level, an offset between the driver ICs may cause a difference between voltages applied to liquid crystals, to cause unevenness in the contrast of a screen and make boundaries visible. This problem will also occur when driver ICs with p-Si TFTs are integrated on a substrate because driver circuits involve offsets.
An object of this invention is to provide a flat panel display capable of displaying good images with suppressed boundaries even if each large block is driven by a plurality of data-line drivers.
A flat panel display according to a first aspect of this invention includes a display panel containing an array substrate, a counter substrate facing the array substrate, and a light modulation layer interposed between the array substrate and the counter substrate. The array substrate includes a matrix of data lines and scan lines arranged on an insulating substrate, pixel switch elements arranged at the intersections of the data and scan lines, and pixel electrodes connected to the pixel switch elements. The flat panel display also includes a data-line driver arranged on the insulating substrate, for providing the data lines with corresponding analog video signals, and a scan-line driver for providing the scan lines with scan signals. The data-line driver at least includes first and second digital-to-analog converters for sequentially converting digital video signals for given data lines into analog video signals in each horizontal scan period. The data lines electrically connected to the first digital-to-analog converter and the data line electrically connected to the second digital-to-analog converter are alternated at intervals of a given number.
In the flat panel display according to the first aspect, the data-line driver includes shift registers that correspond to the first and second digital-to-analog converters, respectively, and operate in parallel.
In the flat panel display according to the first aspect, the pixel switch elements, first and second digital-to-analog converters, and shift registers contain thin-film transistors involving polysilicon active layers.
A flat panel display according to a second aspect of this invention includes a display panel containing an array substrate, a counter substrate facing the array substrate, and a light modulation layer interposed between the array substrate and the counter substrate. The array substrate includes a matrix of data lines and scan lines arranged on an insulating substrate, pixel switch elements arranged at the intersections of the data and scan lines, and pixel electrodes connected to the pixel switch elements. The flat panel display also includes a data-line driver arranged on the insulating substrate, for providing the data lines with corresponding analog video signals, and a scan-line driver for providing the scan lines with scan signals. The data-line driver includes a switch circuit for electrically connecting video bus lines arranged on the insulating substrate to corresponding ones of the data lines, and at least first, second, third, and fourth digital-to-analog converter ICs for sequentially converting digital video signals electrically connected to the video bus lines into analog video signals. The data lines electrically connected to the first digital-to-analog converter, the data lines electrically connected to the second digital-to-analog converter, and the data lines electrically connected to the third digital-to-analog converter are alternately arranged at intervals of a given number.
A flat panel display according to a third aspect of this invention includes a display panel containing an array substrate, a counter substrate facing the array substrate, and a light modulation layer interposed between the array substrate and the counter substrate. The array substrate includes a matrix of data lines and scan lines arranged on an insulating substrate, pixel switch elements arranged at the intersections of the data and scan lines, and pixel electrodes connected to the pixel switch elements. The flat panel display also includes a data-line driver arranged on the insulating substrate, for providing the data lines with corresponding analog video signals, and a scan-line driver for providing the scan lines with scan signals. The data-line driver includes a switch circuit for electrically connecting video bus lines arranged on the insulating substrate to corresponding ones of the data lines, and at least first, second, third, and fourth digital-to-analog converter ICs for sequentially converting digital video signals electrically connected to the video bus lines into analog video signals. The data lines electrically connected to the first digital-to-analog converter, the data lines electrically connected to the second digital-to-analog converter, the data lines electrically connected to the third digital-to-analog converter, and the data lines electrically connected to the fourth digital-to-analog converter are alternately arranged at intervals of a given number.
In the flat panel display according to the third aspect, the first and second digital-to-analog converter ICs provide positive analog video signals based on a reference voltage, and the third and fourth digital-to-analog converter ICs provide negative analog video signals based on the reference voltage.
The switch circuit switches relationships between the video bus lines and the corresponding data lines at predetermined intervals.
In the flat panel display according to the third aspect, the pixel switch elements and switch circuit contain thin-film transistors having polysilicon active layers.
In the flat panel display according to the third aspect, the first to fourth digital-to-analog converter ICs are formed on an external driver circuit board.
When the flat panel displays according to the first to third aspects employ a plurality of data-line drivers for driving one of large blocks divided from a screen, they connect adjacent signal lines to different data-line drivers. This distributes output variations of the data-line drivers, i.e., variations of driver ICs to a whole screen. As a result, no boundary between the driver ICs appears on the screen, thereby properly displaying images.